The well-known Internet network is a notoriously well-known publicly-accessible communication network at the time of filing the present patent application, and arguably the most robust information and communication source ever made available. The Internet is used as a prime example in the present application of a data-packet-network which will benefit from the apparatus and methods taught in the present patent application, but is just one such network, following a particular standardized protocol. As is also very well known, the Internet (and related networks) are always a work in progress. That is, many researchers and developers are competing at all times to provide new and better apparatus and methods, including software, for enhancing the operation of such networks.
In general the most sought-after improvements in data packet networks are those that provide higher speed in routing (more packets per unit time) and better reliability and fidelity in messaging. What is generally needed are router apparatus and methods increasing the rates at which packets may be processed in a router.
As is well-known in the art, packet routers are computerized machines wherein data packets are received at any one or more of typically multiple ports, processed in some fashion, and sent out at the same or other ports of the router to continue on to downstream destinations. As an example of such computerized operations, keeping in mind that the Internet is a vast interconnected network of individual routers, individual routers have to keep track of which external routers to which they are connected by communication ports, and of which of alternate routes through the network are the best routes for incoming packets. Individual routers must also accomplish flow accounting, with a flow generally meaning a stream of packets with a common source and end destination. A general desire is that individual flows follow a common path. The skilled artisan will be aware of many such requirements for computerized processing.
Typically a router in the Internet network will have one or more Central Processing Units (CPUs) as dedicated microprocessors for accomplishing the many computing tasks required. In the current art at the time of the present application, these are single-streaming processors; that is, each processor is capable of processing a single stream of instructions. In some cases developers are applying multiprocessor technology to such routing operations. The present inventors have been involved for some time in development of dynamic multi-streaming (DMS) processors, which processors are capable of simultaneously processing multiple instruction streams. One preferred application for such processors is in the processing of packets in packet networks like the Internet.
In the provisional patent application listed in the Cross-Reference to Related Documents above there are descriptions and drawings for a preferred architecture for DMS application to packet processing. One of the functional areas in that architecture is a packet management unit (PMU) comprising hardware and circuitry for processing data packets.
As described with reference to Ser. No. 09/737,375 in FIG. 1 above the PMU is the part of the processor, known as the XCaliber processor in some instances, that offloads the streaming processor unit (SPU) from performing costly packet header accesses and packet sorting and management tasks, which might otherwise seriously degrade performance of the overall processor.
Packet management functions of the PMU include managing on-chip local packet memory (LPM) for packet storage, uploading packet header information from incoming packets into different contexts registers of the XCaliber processor, and maintaining packet identifiers of the packets currently in process in the XCaliber processor.
There are at least two known means of functionally verifying a PMU. One of these involves using well-known verification techniques, but these are suitable typically for only small designs, and the formal verification technology is not advanced enough. Another is to compare performance of a PMU of unknown quality with an already-verified model. A model can be a completed and functional chip, a model made of pieces of other chips, or a model made of part hardware and part software. A problem here is that, for PMUs of the sort to be tested and verified, there is no verified model, and a first model needs to be verified somehow.
Therefore, what is clearly needed is a reliable and cost-effective method and apparatus for validating packet-managing (PMU) functions in a packet processor, in the absence of an existing and verified model. The present invention teaches apparatus and methods to fill this need.